This invention relates to a semiconductor device and also to a method for fabricating that semiconductor device; and, more particularly, the invention relates to a technique which is effective when applied to fineness and mass storage of a non-volatile semiconductor memory.
There is an electrically rewritable non-volatile semiconductor storage known as a so-called AND-type flash memory, which is set out, for example, in Japanese Laid-open Patent Application No Hei 07-273231. In that publication, the following fabrication method is described as a technique for improving the degree of integration of transistors, called memory cells, existing in a chip.
More particularly, a three-layered built-up film, consisting of a gate oxide film, a first polysilicon layer and a silicon nitride film,is deposited on a semiconductor substrate made of single crystal silicon, and this is followed by patterning the built-up film in the form of stripes. Next, n-type impurity ions are implanted into the semiconductor substrate at portions which have not been covered with the patterned built-up film to form column lines of an n-type impurity semiconductor region in the surface of the semiconductor substrate. Thereafter, after deposition of an oxide film by CVD (Chemical Vapor Deposition), the silicon oxide film formed by the CVD method is etched by anisotropic dry etching to form a side wall spacer on the side walls of the first polysilicon layer and silicon nitride film. Using the first polysilicon layer and the side wall spacers as a mask, grooves are formed in the semiconductor substrate by anisotropic dry etching. In this manner, the n-type impurity semiconductor region is isolated, thereby forming column lines and source lines, respectively. Next, after formation of a silicon oxide film on the surface of the grooves, a second polysilicon layer is attached (deposited) over the entire surface of the semiconductor substrate, and this is followed by etching back the second polysilicon layer by isotropic dry etching until the silicon nitride film is exposed. The surface of the etched-back second polysilicon layer is oxidized to form an element isolation region made of the polysilicon covered with the silicon oxide film. Subsequently, the silicon nitride film is removed, and a third polysilicon layer is further attached and subjected to patterning so as to protect the first polysilicon layer therewith, thereby forming floating gates in parallel with the column lines. Thereafter, an interlayer insulating film and a fourth polysilicon layer are attached, and this is followed by patterning to form column lines made of the fourth polysilicon layer and disposed so as to be vertical to the column lines. Eventually, the first and third polysilicon layers are mutually isolated from each other to form floating gates.
In the AND-type flash memory formed in this way, electrons are stored in the floating gate to constitute a semiconductor device having a non-volatile memory function. Especially, the n-type impurity semiconductor region, which is formed with the first polysilicon layer at opposite sides thereof, serves as a source or drain region. In the method set out above, the processing of the first polysilicon layer and the formation of the element isolation region are performed by use of a one-layer mask pattern, so that no alignment allowance for the gate and the element isolation region is necessary, thereby enabling one to reduce a cell area.
In Japanese Laid-open Patent Application No. Hei 06-77437, there is described a technique concerning a working system of a non-volatile semiconductor memory. In the non-volatile- semiconductor memory set forth in that publication, when electrons are released from a floating gate to write data in a memory cell, a negative voltage is applied to a control gate electrode, while a positive voltage or zero voltage is applied to a drain terminal, thereby describing a technique for selective writing of the data.
Moreover, in Japanese Laid-open Patent Application No. Hei 08-107158, there is described a technique concerning high-speed reading and writing of a non-volatile semiconductor memory. The non-volatile semiconductor memory set out in that publication is fabricated by forming an element isolation region according to the LOCOS (Local Oxidation Of Silicon) method, by forming a first floating gate electrode (lower layer), and source and drain regions, covering the first floating gate electrode with an interlayer insulating film, removing the insulating film by an etching-back method or the CMP (Chemical Mechanical Polishing) method, and forming a second floating gate electrode (upper layer) on the first floating gate electrode.
In Japanese Laid-open Patent Application No. Hei 08-148658, there is described a technique concerning a fabrication method suited for a high degree of integration of a non-volatile semiconductor memory. The non-volatile semiconductor memory set out in that publication is fabricated by patterning a polysilicon layer for floating gates, and forming a polysilicon layer for use as gate electrodes of a peripheral circuit and an insulating film so as to permit them to run on the patterned layer.
However, we have found that the above-stated techniques present the following problems.
1. In the operation of electron withdrawal using the drain terminal, it is necessary to overlap the drain region and the floating gate. Accordingly, the gate length of the memory cell could not be shortened, making it difficult to achieve an intended cell fineness.
2. As a procedure for establishing isolation of memory cells, thermal oxidation is used, so that an excess thermal treating step was added after the formation of a gate oxide film, which made it difficult to ensure the reliability of the gate oxide film. Moreover, it was also difficult to suppress the elongation of the impurity semiconductor region caused during the thermal treating step.
3. A grooved structure is used as a method of forming an isolation region of the memory cells. The polysilicon layer is used as a burying material, so that a difficulty arose concerning the high withstand voltage isolation between the cells.
4. In non-volatile semiconductor memories, such as the AND-type memory flash memories proposed in the above-described techniques, no method of forming memory cells and MOS transistors serving as peripheral circuits and arranged on the same semiconductor substrate is disclosed at all. The fineness of memory cells proceeds through the development of processing techniques. However, a high voltage is used for write and erase operations, and thus, transistors for peripheral circuits are required to have such a specification as to withstand high voltages. For instance, in the fabrication method wherein an impurity semiconductor region of an MOS (Metal-Oxide-Semiconductor) transistor of a peripheral circuit is formed after formation of memory cells, it is difficult to form, on the same substrate, memory cells which should be a shallow junction impurity semiconductor region and the MOS transistor of the peripheral circuit which should have a deep junction structure. More particularly, the impurity semiconductor region of the memory cell should have a shallow junction so as to prevent punch through. On the other hand, the impurity semiconductor region of the high withstand voltage MOS transistor existing in a peripheral circuit permits field relaxation at the junction portion through an annealing step in order to ensure a high withstand voltage. After the formation of the memory cells, if a transistor of the peripheral circuit is formed, an additional annealing step is added to formation of the memory cells. As a result, the punch through resistance is lowered, making it impossible to assure the operation of the transistor having a short gate length.
5. In non-volatile semiconductor memories,such as AND-type flash memories, an MOS transistor for memory cell selection is arranged in a memory mat, but its formation method is not described. On the other hand, with regard to write and erase voltages, the use of a low voltage accompanied by fineness is not available, but operations at a high voltage are required. Accordingly, for the isolation between memory cells and selective transistor units, it is necessary to ensure the isolation withstand voltage.
6. In non-volatile semiconductor memories, including AND-type flash memories, an interlayer insulating film and a control gate electrode material are deposited on the floating gate electrode, and this is followed by processing of a word line electrode (control gate electrode) by photolithography and an etching process. When an electrode pattern is transferred to a photoresist, a halation phenomenon takes place due to the step with the underlying floating gate electrode, thereby causing the pattern form of the photoresist to be partially deformed. According to the fabrication methods of the afore-discussed applications (Japanese Laid-open Patent Nos. Hei 08-107158 and Hei 08-148658), it is possible to some extent to suppress such halation. However, the impartment of a high withstand voltage to the element isolation region is difficult when using these fabrication methods.
An object of the invention is to provide non-volatile semiconductor memory having a structure which is suited for a high degree of integration and its fabrication technique.
Another object of the invention is to increase a memory capacity of a non-volatile semiconductor memory.
A further object of the invention is to provide an operation system of a transistor which enables one to make the gate length of a memory cell as short as possible.
Still another object of the invention is to provide a technique for ensuring reliability of a gate insulating film and for suppressing elongation of an impurity semiconductor region without need of a thermal treatment for the formation of element isolation regions at high temperatures.
Yet another object of the invention is to provide a technique for realizing a high withstand voltage of element isolation regions.
Still another object of the invention is to provide a technique not only of ensuring a high withstand voltage of element isolation regions, but also of realizing a high degree of integration.
Yet another object of the invention is to provide a non-volatile semiconductor memory having a structure which permits high withstand voltage MOS transistors and fine memory cells to be arranged within the same chip and is able to realize the junction of impurity semiconductor regions required for individual transistors and also its fabrication method.
Still a further object of the invention is to provide a technique for reducing, in size, a selective transistor of a memory cell.
Still another object of the invention is to provide a technique for suppressing the halation of exposure light when control gate electrodes of memory cells are patterned.
In the Technical Digest, pp. 61 to 64 of IEDM, 1994, there is described a technique for isolating semiconductor non-volatile elements therebetween by use of grooves formed in a silicon substrate. In accordance with this technique, mention is made, as a filling material for filling the grooves between the elements, of a deposited silicon oxide film (xe2x80x9cLP-CVD filmxe2x80x9d in this literature). The semiconductor non-volatile element consists of a first gate electrode surrounded by an insulating film and a second gate electrode positioned just thereabove.
As stated in the literature, the second gate electrode has to be formed while reflecting the step formed with the first gate electrode. More particularly, processing should be performed while taking into account the difference in height between the upper portion of the first electrode and that electrode. This step may invite a failure in dissolution of photolithography when the second gate electrode is processed, or short-circuiting of adjacent patterns owing to a dry etching failure. Studies has been made in order to reduce the step to an extent as small as possible. Although it appears that planarization between the elements can be realized according to the method described in the literature, the lines of juncture do not completely disappear, since an ordinary deposited oxide film is used for filling in between the elements. The juncture lines are liable to be opened when washed or dry-etched, and once a reduced difference in height appears again, a dry etching failure tends to occur.
To avoid such a phenomenon, there is a method using a filling material in which no juncture line remains. The most popular fluid silicon oxide film is called boron phosphosilicate glass (hereinafter abbreviated as BPSG) which contains very high concentrations of boron and phosphorus. When thermally treated at approximately 850xc2x0 C., BPSG has the property of exhibiting high fluidity. This is one of the materials which is suitable for reducing a difference in height of a fine width. However, the solubility in hydrofluoric lacid, which is used in a cleaning step that is essential for the manufacture of semiconductor devices, is greater by several times than that of a non-doped silicon oxide film. Accordingly, BPSG, which is employed for filling between the elements and planarization undergoes considerable attack during the cleaning process, thereby causing a great difference in height once again.
Still another object of the invention is to provide a technique for solving the step problem wherein there is used a material having an etching resistance sufficient to permit hydrofluoric acid to be employed in a cleaning step.
The above and other objects, and novel features of the invention will become apparent from the description in the present specification and from the accompanying drawings.
Among the features disclosed in the present application, the outlines of typical ones are briefly described as follows.
In order to achieve the above objects, the structures of non-volatile semiconductor memories and their fabrication methods are disclosed below.
(1) A method of fabricating a semiconductor device according to the invention comprises the steps of (a) depositing a first conductive film on a memory cell-forming region and a peripheral circuit region of a semiconductor substrate, (b) etching the first conductive film of the memory cell-forming region to form a first conductor pattern, (c) polishing an insulating film deposited on the first conductor pattern and the peripheral circuit-forming region to form a first insulating film on a non-patterned portion of the first conductor patterns, (d) after the step (c), forming a second conductor pattern on the first insulating film and the first conductor pattern; and (e) subjecting the first conductor pattern and the second conductor pattern to patterning to form a floating gate electrode of memory cells.
It will be noted that the surface position of the first insulating film beneath the second conductor pattern is so arranged as to be higher than that of the first conductor pattern.
A method of fabricating a semiconductor device according to the invention comprises the steps of etching a first conductive film formed on a semiconductor substrate to form a first conductor pattern, (b) polishing an insulating film deposited on the first conductor pattern to form a first insulating film on non-patterned portions of the first conductor patterns, (c) after the step (b), forming a second conductor pattern on the first insulating film and the first conductor pattern, and (d) patterning the first conductor pattern and the second conductor pattern to form a floating gate electrode of memory cells wherein the surface position of the first insulating film beneath the second conductor pattern is so arranged as to be higher than the surface position of the first conductor pattern.
It will be noted that the first conductor pattern is formed by depositing a second insulating film on the first conductor and etching the second insulating film and the first conductive film, and the step of forming the first insulating film includes, after polishing of the insulating film, etching the insulating film to the second insulating film.
Moreover, the second insulating film is deposited on the first conductive film, and the second insulating film and the first conductive film are both etched to form the first conductor pattern. In the step of forming the first insulating film, the insulating film is polished to the second insulating film. It is to be noted that the second insulating film of this case can serve as a stopper layer when polished.
In addition, the method further comprises, prior to the step of forming the first insulating film, the steps of forming side wall spacers at the side walls of the first conductor pattern, and etching the substrate to self-alignedly form a groove relative to the side wall spacers.
(2) The semiconductor device of the invention has first MISFET""s which constitute memory cells. The first MISFET""s include a first floating gate electrode formed on a main surface of a semiconductor substrate through a gate insulating film, a second floating gate electrode formed on and electrically connected to the first floating gate electrode, a control gate electrode formed on the second floating gate electrode through an interlayer insulating-film, and a pair of semiconductor regions formed within the semiconductor substrate and serving as source/drain regions, wherein the first MISFET""s are isolated, with a first isolation region, from adjacent first MISFET""s adjoining along a first direction, the insulating film is so formed that it has a thickness greater than that of the first floating gate electrode on the first isolation region, the second floating gate electrode is formed to extend on the insulating film, and the surface position of the insulating film is higher than that of the first floating gate electrode.
Further, the semiconductor device of the invention is one which has first MISFET""s and second MISFET""s. The first MISFET constituting a memory cell includes a floating gate electrode formed on a main surface of a semiconductor substrate through a gate insulating film, a control gate electrode formed on the floating gate electrode through an interlayer insulating film, and the second MISFET includes a gate electrode formed on the main surface of the semiconductor substrate through a gate insulating film. The first MISFET""s are arranged in the form of an array, and the first MISFET""s are isolated from adjacent first MISFET""s by means of a first isolation region along a first direction, and the surface position of an insulating film formed on the first isolation region is substantially uniform between the first MISFET""s arranged in the form of an array and is higher than the surface position of an insulating film formed on a second isolation region.
It will be noted that in the above semiconductor device, the insulating film is buried between the side wall spacers formed on the side walls of the first floating gate, and a semiconductor region is formed below the side wall spacers.
In the semiconductor device, the first isolation region has such a structure that the insulating film is buried in the groove of the semiconductor substrate, which is formed self-alignedly to the side wall spacers formed on the side surfaces of the first floating electrodes.
Moreover, in the semiconductor device, one of the paired semiconductor regions serving as the source/drain regions of the second MISFET is electrically connected to the semiconductor region of the first MISFET, and the second MISFET""s are isolated from each other by means of a second isolation region, and the first and second isolation regions have such a structure that an insulating film is buried in grooves of the semiconductor substrate which are formed self-alignedly to the side wall spacers formed on the side surfaces of the first floating gate electrode and the gate electrode of the second MISFET.
In the semiconductor device, the gate electrode of the second MISFET is made of materials which constitute, at least, the first floating gate electrode, second floating electrode and control gate electrode, and the second floating electrode and the control gate electrode are electrically connected. In this connection, the second floating gate electrode and the control gate electrode may be connected via an opening formed in the interlayer insulating film.
Furthermore, the semiconductor device of the invention is one which has first MISFET""s constituting memory cells and second MISFET""s. The first MISFET constituting a memory cell includes a first floating electrode formed on a main surface of a semiconductor substrate through a gate insulating film, a second floating gate electrode formed on and electrically connected to the first gate electrode, a control gate electrode formed on the second floating gate electrode through an interlayer insulating film, and a pair of semiconductor regions formed within the semiconductor regions formed within the semiconductor substrate and serving as source.drain regions, and the first MISFET is isolated, with a first isolation region, from an adjacent first MISFET adjoining along a first direction. The second MISFET has a first gate region made of materials which constitute the gate insulating film, the first floating gate electrode, the second floating gate electrode, the interlayer insulating film and the control gate electrode, and a second gate region made of materials which constitute the interlayer insulating film and the control gate electrode, both disposed along the direction of the gate length. The semiconductor region, which acts as one of the source/drain regions of the second MISFET, is electrically (connected) to one semiconductor region of the first MISFET and is arranged to extend to the lower portion of the first gate region. The channel region of the second MISFET is formed within the substrate at the lower portion of the second gate region and is formed between the semiconductor regions serving as the source/drain regions of the second MISFET. In this case, the control gate electrode of the first MISFET is formed integrally with a word line formed to extend in the first direction, and the one of semiconductor regions of the second MISFET is formed integrally with one of semiconductor regions of a first MISFET provided adjacently to a second direction which is vertical to the first direction, and the other semiconductor region of the second MISFET may be electrically connected to a data line.
Further, the semiconductor device of the invention is one which has first MISFET""s constituting memory cells. The first MIFET includes a first floating gate electrode formed on a main surface of a semiconductor substrate via a gate insulating film, a control gate electrode formed on the upper portion of the first floating gate electrode via an interlayer insulating film, and a pair of semiconductor regions formed within the semiconductor substrate and serving as source/drain regions. The channel region of the first MISFET is arranged between the paired semiconductor regions within the substrate, and the paired semiconductor regions of the first MISFET are arranged to have a symmetric structure. In this arrangement, information is written and erased by charging and discharging electrons between the entire surface of the channel region and the first floating gate electrode by tunneling through the gate insulating film.
In the semiconductor device, for the erase operation wherein electrons are discharged from the first and second floating gate electrodes to the substrate by tunneling through the gate insulating film, a first voltage is applied to the control gate electrode, and the semiconductor region of the first MISFET is set at the same potential as the semiconductor substrate portion beneath the first floating gate electrode and is set at a voltage lower than a first voltage.
Moreover, for the write operation in the semiconductor device wherein electrons are discharged from the substrate to the first floating gate electrode by tunneling through the gate insulating film, a second voltage of a polarity different from that of the first voltage is applied to the control gate electrode, and the semiconductor region of a selected first MISFET is set at the same potential as the semiconductor substrate portion beneath the first floating gate electrode, thereby reversing the channel region. At the same time, a third voltage having the same polarity as the second voltage is applied to the semiconductor region of a non-selected first MISFET so that the voltage between the channel region and the control gate electrode is rendered lower than a potential between the channel region of the selected first MISFET and the control gate electrode. It should be noted that when the control gate voltage added as the second voltage has three or more voltage levels and the change of a threshold value of the first MISFET logically corresponds to individual voltage levels on the basis of the difference in charge quantity injected into the floating gate electrode corresponding to the voltage level, information of two bits or more can be memorized in one memory cell. Further, for the writing of information in a memory cell, the information can be written while successively shifting from a writing operation at the highest second voltage to writing operations at lower second voltages.
For the read out of information from a memory cell, the information can be read out while successively shifting from detection of a threshold value corresponding to the quantity of charges injected at the lowest second voltage to detection of threshold values corresponding to the quantities of charges injected at higher second voltages.
In the above semiconductor device, the channel region of the first MISFET may be arranged between the paired semiconductor regions in the second direction vertical to the first direction.
The channel region of the first MISFET may be arranged between the paired semiconductor regions in the first direction.
Moreover, in the semiconductor device, the paired semiconductor regions of the first MISFET may be arranged to have a symmetrical structure.
(3) A method of fabricating a semiconductor device according to the invention which comprises a word line formed to extend in a first direction, local data line and a local source line made of a semiconductor region formed to extend in a second direction with a semiconductor substrate, and first MISFET""s and second MISFET""s, the first MISFET""s, which constitute memory cells, including a first floating gate electrode formed on a main surface of the semiconductor substrate through a gate insulating film, a second floating gate electrode formed on and electrically connected to the first floating gate electrode, a control gate electrode formed on the second floating electrode through an interlayer insulating film, and a pair of semiconductor regions formed within the substrate and serving as source/drain regions, the second MISFET""s including a gate electrode formed on the main surface of the semiconductor substrate through a gate insulating film and semiconductor regions formed within the semiconductor substrate, serving as source/drain regions and electrically connected to one of the semiconductor regions of the first MISFET""s wherein first MISFET ""s are isolated such that first MISFET""s adjoining in a first direction are subjected to isolation with a first isolation region and second MISFET""s are subjected to isolation with a second isolation region. The method comprises the steps of (a) successively depositing a gate insulating film, a first conductive film and a first insulating film on a semiconductor substrate and patterning the first insulating film and the first conductive film in a striped column pattern, (b) forming a side wall spacer on side walls of the column pattern, (c) etching the semiconductor substrate self-alignedly to the side wall spacers to form a groove in the semiconductor substrate, (d) depositing a second insulating film on the semiconductor substrate including the inside of the groove and removing the second insulating film to the level of the first insulating film for planarization thereby forming first and second isolation regions, (e) after the step (d), removing the first insulating film to expose the surface of the first conductive film, (f) forming a second conductive film in contact with the surface of the first conductive film to cover the first conductive film in a direction of extension of the column pattern, and (g) successively depositing an interlayer insulating film and a third conductive film on the second conductive film and patterning the third conductive film, the interlayer insulating film and the first and second conductive films in a direction vertical to the extending direction of the column pattern.
The method of fabricating a semiconductor device according to the invention is used to fabricate a semiconductor device including a first floating gate electrode formed on a main surface of a semiconductor substrate through a gate insulating film, a second floating gate electrode formed on and electrically connected to the first floating gate electrode, a control gate electrode formed on the second floating gate electrode through an interlayer insulating film, and a pair of semiconductor regions formed within the semiconductor substrate and serving as source/drain regions. The method comprises (a) successively depositing a gate insulating film, a first conductive film and a first insulating film on a semiconductor substrate and patterning the first insulating film and the first conductive film in a striped column pattern, (b) forming a side wall spacer on side walls of the column pattern, (c) after the step (b), depositing a third insulating film on the semiconductor substrate, (d) removing the third insulating film to the first insulating film for planarization, (e) removing the first insulating film to expose the surface of the first conductive film and forming a second conductive film in contact with the surface of the first conductive film to cover the first conductive film in a direction of extension of the column pattern, and (f) successively depositing an interlayer insulating film and a third conductive film on the second conductive film and patterning the third conductive film, the interlayer insulating film and the first and second conductive films in a direction vertical to the extending direction of the column pattern.
Further, the method for fabricating a semiconductor device according to the invention comprises the steps of (a) successively depositing a gate insulating film, a first conductive film and a first insulating film on a semiconductor substrate and patterning the first insulating film in a striped column pattern, (b) after the step (a), subjecting the semiconductor substrate to etching self-alignedly to the first insulating film to form a groove in the semiconductor substrate, (c) depositing a second insulating film on the semiconductor substrate including the groove surface and removing the second insulating film to the first insulating film for planarization, (d) removing the first insulating film to expose the surface of the first conductive film and forming a second conductive film in contact with the surface of the first conductive film to cover the first conductive film in a direction of extension of the column-pattern, and (e) successively depositing an interlayer insulating film and a third conductive film on the second conductive film and patterning the third conductive film, the interlayer insulating film and the first and second conductive films in a direction vertical to the extending direction of the column pattern.
In the above fabrication method, the first floating gate electrode is constituted-of the first conductive film, the second floating gate electrode is constituted of the second conductive film, and the gate control electrode is constituted of the third conductive film, and after the patterning of the third conductive film, and after of semiconductor regions serving as source/drain regions can be formed.
The surface position of the third insulating film beneath the second conductive film may be formed at a level which is the same as or higher than the surface position of the first conductive film.
In the step (d), polishing of the third insulating film ensures planarization.
Moreover, the first insulating film can be used as a stopper layer. In the step (d), after planarization by polishing of the third insulating film, the third insulating film can be removed by etching to the first insulating film.
The patterning of the striped column pattern in the step (a) is performed with respect to a memory cell-forming region in such a way that other regions have the first conductive film and the first insulating film left thereon.
Moreover, a third MISFET is formed wherein semiconductor regions serving as source/drain regions of the third MISFET are formed prior to the formation of a semiconductor region.
The method further comprises the step of forming a first-layer wire, and the first-layer wire in a memory cell-forming region is provided in the form of lattices, and an interlayer insulating film between the first-layer wire and a second-layer wire formed thereon is planarized by the CMP method.
Further, the method of fabricating a semiconductor device according to the invention comprises the steps of (a) depositing a first conductive film on a first MISFET-forming region and a second MISFET-forming region of a semiconductor substrate, (b) etching the first conductive film in the first MISFET-forming region to form a first conductive pattern, (c) polishing an insulating film deposited on the first conductor pattern and the first conductive film of the second MISFET-forming region to form a first insulating film between the first conductor patterns, and (d) after the step (c), removing the first conductive film of the second MISFET-forming region.
The above fabrication method may further comprise, after the step (d), the step of forming a gate insulating film and a gate electrode in the second MISFET region.
The method may further comprise, after the step (c) the step of removing a second conductor pattern on the first insulating film and the first conductor pattern wherein the first conductor pattern and the second conductor pattern constitute a floating gate electrode of a memory cell and the surface position of the first insulating film beneath the first conductor pattern is arranged to be higher than the surface position of the first conductor pattern.
(4) A semiconductor device of the invention is one which has first MISFET""s constituting memory cells. The first MISFET includes a first floating gate electrode formed on a main surface of a semiconductors substrate through a gate insulating film, a control gate electrode formed on the upper portion of the first floating gate electrode via an interlayer insulating film, a pair of semiconductor regions formed within the semiconductor substrate and serving as a source.drain region wherein first MISFET""s adjoining in a first direction are subjected to isolation with a first isolation region, and the first isolation region has a structure in which an insulating film is buried in grooves of the semiconductor substrate, and wherein the surface position of the insulating film is higher than the main surface of the semiconductor substrate and the channel region of the first MISFET is positioned between the paired semiconductor regions in a second direction vertical to the first direction.
The semiconductor device may be so arranged that a second floating gate electrode is formed on the upper portion of the first floating gate electrode and is electrically connected to the first floating gate electrode, an interlayer insulating film is formed on the second floating gate electrode so that the second floating gate electrode extends over the upper surface of the insulating film, and the upper surface of the insulating film is made higher than the upper surface of the first floating gate electrode.
Moreover, a side wall spacer may be formed on side surfaces of the first floating gate electrodes, under which grooves are formed self-alignedly relative to the side wall spacers.
Alternatively, the groove may be formed self-alignedly relative to the side surfaces of the first floating gate electrode.
When using the above measures, the objects of the invention can be achieved with the following features.
Firstly, write operation to memory cells and erase operations are performed through full charge and discharge of electrons via the gate insulating film provided between the floating gate and the semiconductor substrate, so that a conventional overlapped portion of a floating gate electrode and a drain region becomes unnecessary. This enables one to reduce the area of a memory cell, thus making it possible to achieve a high degree of integration of a non-volatile semiconductor memory.
Secondly, memory cells along the direction of a data line can be divided into blocks by means of selective transistors. At the time of a write operation, selective transistors in a non-selected block are turned off, so that application of an unnecessary data line voltage to memory cells can be inhibited in the non-selected block. Thus, rewrite of unintentional information to non-selected memory cells (disturb phenomenon) can be prevented, thus improving the reliability of the non-volatile semiconductor memory.
Thirdly, the isolation region for a memory cell and a selective transistor is arranged to have a shallow groove isolation structure, so that excess thermal hysteresis on the gate oxide film can be prevented and the reliability of an oxide film constituting the gate insulating film can be improved. Moreover, the isolation resistance is also improved.
Fourthly, the impurity semiconductor region of MOS transistors in a peripheral circuit is formed prior to the formation of memory cells. Accordingly, the memory cells do not suffer any thermal hysteresis owing to the formation of the memory cells. Accordingly, the memory peripheral MOS transistors. The impurity semiconductor region of the MOS transistors of the peripheral circuit is formed at adequately high temperatures, thereby ensuring the formation of a deep junction, enabling one to obtain a structure suitable for transistor operations at high voltages. On the other hand, the impurity semiconductor region of the memory cell is formed with a shallow junction, thereby making it possible to keep a high resistance to punch through. Such a shallow junction impurity semiconductor region of the memory cell does not subsequently undergo excess thermal hysteresis so that excessive diffusion of an impurity does not take place, and thus, a shallow junction keeps its structure as initially formed.
Fifthly, an underlying layer is flattened prior to the formation of the second floating gate electrode, and the processing precision of the second floating gate electrode and the word line is improved. More particularly, when the second floating gate electrode is patterned, the underlying layer is flattened, so that scattering of exposure light, which reflects the irregularities of the underlying layer, does not take place. This contributes to the improvement in exposure precision, thereby improving the processing precision of the non-volatile semiconductor memory to make a high degree of integration easy.
In this application, in order to solve the above problems, there are disclosed a semiconductor device and a method for making same.
The semiconductor device of the invention comprises a plurality of semiconductor elements formed on the same semiconductor substrate, a fluid silicon oxide film containing phosphorus or boron, which is filled between electrodes of the semiconductor substrate and wherein nitrogen is introduced to the surface of the fluid oxide film.
The electrodes may be provided as a floating gate electrode of a semiconductor non-volatile memory.
The method of fabricating a semiconductor device according to the invention comprises filling a phosphorus or boron-containing fluid silicon oxide film between electrodes of a plurality of semiconductor elements formed on the same semiconductor substrate where the electrodes are made of polysilicon, and subjecting the surface of the fluid oxide film to thermal treatment in an atmosphere of ammonia.
The electrodes may be provided as a floating gate electrode of a semiconductor non-volatile memory.
In the practice of the invention, in order to improve the resistance to liquid cleaning, BSPG is heated in an atmosphere of ammonia. BSPG is nitrided to a depth of approximately 100 nm from the surface. By this measure, the solubility velocity in hydrofluoric acid can be suppressed to a level approximately equal to that of an non-doped silicon oxide film, thus enabling the step between the elements to be flattened.
FIG. 110 shows an effect of improving the solubility velocity of BPSG in hydrofluoric acid (1:100 dilutionwith water) The etching rate of BPSG, which has been treated at 850xc2x0 C. in an atmosphere of nitrogen, is approximately at 45 nanometers/minute irrespective of the treating time. On the other hand, where BPSG is subjected to thermal treatment (i.e. nitriding treatment) in an atmosphere of ammonia for 10 minutes or more, its etching rate is reduced to approximately 5 nanometers/minute. An etching rate, in the case where a non-doped oxide film (deposited by a chemical vapor phase growth process) is nitrided, is set out, with its value being almost the same as that attained by thermal treatment in an atmosphere of nitrogen. As shown in the figure, the etching rate of a nitrided film of BPSG can be reduced to half of a non-doped, deposited oxide film.
FIG. 111 shows an effect of a treating temperature in the case where it is subjected to thermal treatment in an atmosphere of ammonia for 20 minutes. It has been found that the etching rate is almost the same as that of a non-doped, deposited oxide film for i treatment at 750xc2x0 C. and can be reduced to a lower level for 800xc2x0 C. or higher.
From these experiments, it will be seen that the etching rate of BPSG, which has been nitrided at a temperature of 750xc2x0 C. or more, with 1:100 dilution of hydrofluoric acid, can be suppressed to a level lower than that of a non-doped, deposited oxide film, i.e. to a level approximately of 5 nanometers/minute. This value is sufficient to keep a flat step between elements.
The effects attained by typical ones among the features disclosed hereinafter will be described below in a brief summary.
(1) Since a shallow groove structure using a buried insulating film is used to effect isolation between memory cells and selective transistors, a lowering of the isolation withstand voltage in the fine region is presented, and a variation in threshold value of the selective transistors can be reduced.
(2) Memory cells in a memory mat can be segmented by means of the selective transistors, thereby improving the disturb resistance of the memory cells.
(3) An information rewriting system where electric charges are injected and released on the entire surfaces of the channels, so that a shallow junction impurity semiconductor region structure is enabled. As a result, a cell operation in a fine region becomes possible. In addition, the degradation of gate oxide films caused by rewriting can be reduced.
(4) The impurity semiconductor region of high withstand voltage MOS transistors is formed prior to the formation of an impurity semiconductor region of memory cells having fine gate structures, thereby preventing unnecessary heat diffusion to the memory cells to ensure the operation in the fine gate region.
(5) After formation of the first floating gate electrode, a buried layer consisting of a silicon oxide film, which is formed by a CVD process, in a substrate region between the gate electrodes, is planarized, so that fine processing without involving dimensional variations becomes possible in the processing of the second floating gate electrodes and in the processing of word lines intersecting at right angles with the floating gate electrodes.
(6) A flat element structure is realized by burying irregularities derived from the difference in height between elements, and an etching resistance of the insulating film realizing the planarization can be improved. As a result, all processing failures derived from the difference in height between the elements can be fully suppressed.